The biomedical implant and remote environmental sensor testbeds both require power-efficient electronics to achieve acceptable size, battery life, and operating temperatures. The goal of this thrust is to develop techniques that will significantly lower the power dissipation of digital and analog circuits. The approach taken encompasses device design; low-level analog and digital circuits; module, chip, and board-level architectures; design flow; and software compilation. A specific goal is to develop for the biomedical and environmental testbeds, low-power mixed-signal microcontrollers that integrate as much of the interface as is practical for the needed solid-state sensors and actuators. In addition to the microprocessor core, these ICs will include analog-to-digital converters, programmable serial and parallel interfaces, memory, on-chip clock generation, a DSP module, and a power-aware C language code compiler for the WIMS processor.

Most of the past low-power circuit work has been in the digital domain, aimed at portable computing and communications applications. The ERC testbeds call for much lower power per computation and for low-power analog circuitry as well. The Micropower Integrated Circuit Thrust is building on the low-power work being done by others throughout the industry, employing static logic, low power-supply voltage, gated clocks, low gate and source-drain leakage circuits, and power-down modes. This project is pushing such techniques beyond the state-of-the-art, employing subvolt power supplies in 0.18 through 0.065µm bulk and SOI CMOS processes with a wide variety of circuit techniques being developed to reduce both active and standby power.

Several approaches being taken in this project set it apart from the work of others. It is focused on quantitative techniques for making architectural trade-offs to minimize microcontroller power, development of very-low-voltage analog circuit techniques, and co-development of the microcontroller and compiler. By addressing power considerations over the full range of design levels, from architecture to interconnect, the project will reduce power to the point required by the WIMS testbeds.